Energy-Aware RISC-V SoC with Integrated AI Accelerator for Edge Computing Applications

Edge intelligence requires processing that is very efficient on-device, with the capability to run neural loads with very tight requirements in terms of energy and latency. A 16x16 quantized tensor accelerator and multi-bank on-chip memory subsystem is made energy-aware with an energy-efficient RISC-V System-on-Chip to meet these requirements. Some of the architecture features used are fused micro-operations, dataflow-based scheduling, workload-based DVFS, and quantized systolic computation. Based on experimental assessment, it has achieved significant improvements: 9.8 TOPS/W energy efficiency, 62% drop in off-chip memory access, 17.4% fall in micro-op energy, 94.7% PE utilization, 31% idle-power, and 11.3 ms edge workloads inference latency. These findings prove significant changes in the computational density, dataflow performance, and the responsiveness of the system. The proposed SoC provides a scalable platform to support advanced edge-AI applications with the need to execute high-performance, low-power, and real-time inferences.