Fault Tolerant Probabilistic VLSI Design for Reliable Deep Learning Hardware Accelerators

Designing reliable deep learning accelerators is critical for deployment in fault-prone edge environments and safety-critical applications. This paper introduces a novel Fault-Tolerant Probabilistic Deep Learning Accelerator (FTPDLA) that integrates stochastic logic design, adaptive redundancy, and runtime reliability control into the VLSI pipeline. The architecture is based on probabilistic CMOS (PCMOS) gates, logic mapping that is delay sensitive, and temporal execution techniques to overcome timing violations, soft errors, and transient bit flips without adding much hardware overhead. Benchmark models of FTPDLA using CNN-MNIST, ResNet-18, and Transformer networks proved that the network was able to achieve up to 98.9% accuracy with injected fault conditions, and an average increase of over 45% in resilience compared to conventional ECC and deterministic accelerators. The energy overhead was restricted to 25.6 and area impact had been restricted to less than 14.2. The model also did not have high neuron activation drift and repeated itself on other datasets such as CIFAR-10 and ImageNet. These findings confirm the suggested architecture as a strong and useful alternative to reliable inference where volatile hardware is involved. FTPDLA prepares the ground to future implementation of scalable, energy-efficient, and self-healing AI accelerators in edge computing, autonomous systems, and healthcare equipment with a need to have reliable real-time execution.